1. Field of the Invention
The present invention relates to solid state switching devices. More particularly, the present invention relates to a two-transistor, zero-power, electrically-alterable non-volatile latch element. Typical environments for the present invention include using the switch to control a pass transistor for user-programmable circuit applications.
2. The Prior Art
The problem of providing non-volatile latch elements has been addressed in the prior art. Several solutions have been proposed.
U.S. Pat. No. 4,132,904 to Harrari, discloses a static-RAM-like structure employing a cross-coupled CMOS latch in which the N-Channel transistors are provided with floating gates which may be programmed to impart a desired state to the latch. While the Harrari circuit does provide a non-volatile latch which provides complementary data which can be reprogrammed, it requires high-voltage n-well structures and provides indeterminate data on first powerup. In addition, the floating gate structures are prone to the well known read-disturb phenomenon by which repeated read operations can degrade the stored data.
U.S. Pat. No. 4,300,212 to Simko discloses a non-volatile static RAM circuit. It employs a very large cell size including at least eight transistor devices, some of which are complicated semiconductor structures. U.S. Pat. No. 4,858,185 to Kowshik et al. discloses a structure employing a CMOS non-volatile latch. While the Kowshik et al. latch does provide a non-volatile latch which provides complementary data which can be reprogrammed, can assume a known state on powerup and does not require high-voltage n-well technology, it requires a very large cell size employing ten transistors as well as other structures.
It is therefore an object of the present invention to provide a non-volatile latch element which overcomes some of the shortcomings of the prior art.
Another object of the present invention is to provide a non-volatile latch element which employs a small cell size.
Another object of the present invention is to provide a non-volatile latch element which employs a minimum number of transistor devices.
A further object of the present invention is to provide a non-volatile latch element which does not require high-voltage n-well technology.
Yet another object of the present invention is to provide a non-volatile latch element which has improved read disturb immunity.
It is a further object of the present invention to provide a non-volatile latch element which assumes a known state on powerup.